InCipher™ Inline Memory Encryptor

PRODUCT BRIEF BOOKASIC | ALTERA | MICROSEMI | XILINX

Athena delivers external memory protection for your SoC application with the InCipher inline memory encryptor cores. The InCipher M1/M2 inline memory encryptor cores provide secure random access to data and programs stored in vulnerable bulk memory devices, whether these devices are RAM or non-volatile memories, such as Flash. This enables your application to execute using the protected memories directly – without depending on the application to load sensitive code and data into on-chip memories. Using Athena’s mature portfolio of TeraFire® security solutions, the InCipher M1 provides cryptographic confidentiality for sensitive programs and data, while the InCipher M2 adds authentication for applications requiring greater tamper resistance.

Product Description

The InCipher cores are designed to be placed between the host bus interface and the external memory controller. In typical applications, the external memory may be DDRn, conventional Flash, or even QSPI Flash. InCipher works with any memory technology, since the InCipher cores inter-operate with external memory controllers at the bus transactional level.

InCipher cores mitigate the latency and throughput limitations of inline random access memory encryption by offering the choice of single or multi-core AES solutions to decrease latency and increase throughput. The choice of single or multi-core AES solutions allows each InCipher implementation to be tuned to the specific requirements of the application. InCipher further increases the performance of your system by implementing a configurable N-way, write-back cache. With the InCipher integrated cache, your application can actually achieve higher throughput and lower latency than it would without InCipher. Using standard bus interfaces, integration is a snap, and, since the InCipher acts as a physical cache between the system and the memory controller, there are no cache coherency challenges.

Bus Interfaces

The InCipher M1/M2 cores are available with a choice of AHB-32, AHB-64, AXI-32, AXI-64, or AXI-128 buses and can support integration in a range of applications from small micro-controllers to the latest full-featured microprocessors running in multi-core configurations.

Features:

  • NEW- SCA Countermeasures
  • Secure external memory random access using encryption and authentication
  • Protects virtually any standard external memory: DDRn, Flash, QSPI, etc.
  • Leverages mature TeraFire AES products
  • Supports both 128-bit and 256-bit key strengths
  • Available in single and multiple AES core configurations
  • Integrated configurable N- way write-back cache
  • Suitable for virtually any implementation technology
  • AMBATM AHB and AXI bus interfaces available
  • Simple/differential power analysis (SPA/DPA) resistance available

Benefits:

  • Eliminates the need for custom complex data/code paging to on-chip memories
  • Enables existing applications to run unchanged directly from external memories
  • Enhanced tamper resistance

Applications

  • Embedded secure processing

Available Deliverables

  • Simulation model (Verilog or VHDL)
  • Synthesizable RTL ( Verilog or VHDL) and scripts
  • Targeted, timing closed netlist
  • Verification suite
  • Documentation

Support

  • 12 months maintenance and support included