Secure Hash Algorithm (SHA)


Athena delivers Secure Hash Algorithms (SHA) as semiconductor intellectual property (IP) cores. Whether your application demands high-performance cryptographic hashing or the power savings of a dedicated core, Athena’s SHA cores deliver. Athena SHA cores are compliant with FIPS 180-2 and can accept data input rates ranging from 2.9 Gbps to over 7.5 Gbps at 500 MHz, with even higher frequencies and corresponding throughputs available.

Product Description

Dedicated SHA family cores feature 32-bit and/or 64-bit data input ports and a full-width message digest output for maximum throughput and minimum latency. Input/output flow control simplifies system integration, and standard bus interfaces are available for applications that require bus connectivity. Context save and reload, automatic message padding, and HMAC features address a range of use cases. SHA support is also available in the EXP-F5200B cryptography microprocessor.


  • NEW- SCA Countermeasures
  • FIPS 180-2 compliant SHA
  • SHA-1 and SHA2-224/256/ 384/512 support in product family
  • Multi-Gbps performance
  • Higher performance available
  • Full-width message digest output
  • Rapid context switching
  • Microprocessor bus inter- faces available
  • SHA support also available in TeraFire F5200 cryptography microprocessor
  • Portable to any technology library
  • Silicon proven
  • Fast delivery
  • Easy integration into any SoC design


  • Full-width data ports maximize performance, minimize latency


  • Encrypted data storage
  • Secure communications
  • Secure processing
  • IPsec acceleration
  • E-commerce
  • VPN
  • Financial Transactions

Available Deliverables

  • Simulation model (Verilog or VHDL)
  • Synthesizable RTL ( Verilog or VHDL) and scripts
  • Targeted, timing closed netlist
  • Verification suite
  • Documentation


  • 12 months maintenance and support included